1. Field of the Invention
The present invention relates generally to memory circuits, and more particularly to content addressable memory (CAM) circuits having a continuous search function.
2. Description of the Related Art
Modern computer systems and computer networks utilize memory devices for storing data and providing fast access to the data stored therein. A content addressable memory (CAM) is a special type of memory device often used for performing fast address searches. For example, Internet routers often include a CAM for searching the address of specified data. Thus, the use of CAMs allow routers to perform address searches to facilitate more efficient communication between computer systems over computer networks. Besides routers, CAMs are also utilized in other areas such as databases, network adapters, image processing, voice recognition applications, etc.
Conventional CAMs typically include a two-dimensional row and column content addressable memory core array of cells. In such an array, each row typically contains an address, pointer, or bit pattern entry. In this configuration, a CAM may perform xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d operations at specific addresses as is done in conventional random access memories (RAMs). However, unlike RAMs, data xe2x80x9csearchxe2x80x9d operations that simultaneously compare a bit pattern of data against an entire list (i.e., column) of pre-stored entries (i.e., rows) can only be performed by CAMs.
FIG. 1A shows a simplified block diagram of a conventional CAM 10. The CAM 10 includes a data bus 12 for communicating data, an instruction bus 14 for transmitting instructions associated with an operation to be performed, and an output bus 16 for outputting a result of the operation. For example, in a search operation, the CAM 10 may output a result in the form of an address, pointer, or bit pattern corresponding to an entry that matches the input data.
Although conventional CAMs are becoming more powerful in their ability to perform searches more rapidly, conventional CAMs suffer in that search operations must be stopped in order to allow for maintenance operations (e.g., read and write operations) on the CAM memory. As a result, even the fastest CAMs must stop their search operations for one or more cycles until the maintenance operations are complete.
In view of the foregoing, what is needed is CAM circuitry that enables continuous searching while also enabling maintenance operations to set up the CAM core for future searches.
The present invention fills this need by providing a content addressable memory (CAM) architecture having a separate search port and a maintenance port, the search port being configured to perform uninterrupted searches on each cycle and the maintenance port being configured to perform maintenance operations without interrupting the searches. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a content addressable memory (CAM) is disclosed. The CAM includes a search port for performing search operations at each clock cycle and a maintenance port for writing and reading data to address locations of the content addressable memory. An interlock signal is also provided and is communicated from the search port to the maintenance port to establish when writing and reading of data is to be performed to the content addressable memory so that the search operations continue uninterrupted at each clock cycle. Preferably, the interlock signal is communicated at an end of a search operation and at a beginning of a search pre-charge operation. The maintenance port is configured to set-up a writing operation at a beginning of a clock cycle and execute the write operation at the end of the search operation and the beginning of the search pre-charge (or recovery) operation. Another preferred aspect of this embodiment is that search operations can be deselected at any time, yet any desired writing and reading operation can still be executed. At anytime therefore, the search operations can resume operation at each cycle, without being affected by a read or write operation.
In another embodiment, a two port content addressable memory (CAM) is disclosed. The two port CAM includes a maintenance port and a search port. Further included is a plurality of sub-block memory columns being defined between the maintenance port and the search port. An interlock signal is also provided to communicate interlock signals from the search port to the maintenance port to signal when reads and writes are to be performed by the maintenance port without interrupting the search port from executing a search operation on every clock cycle during a desired search operation. Preferably, the interlock signal is communicated at an end of a search operation and at a beginning of a search pre-charge operation. In another preferred feature, the maintenance port is configured to set-up a writing operation at a beginning of a clock cycle and execute the write operation at the end of the search operation and the beginning of the search pre-charge operation.
In yet another embodiment, a content addressable memory chip is disclosed. The chip includes: (a) a first macro including a first set of 8 cores; (b) a second macro including a second set of 8 cores; (c) a first maintenance port integrated to a first side of the first set of 8 cores; (d) a second maintenance port integrated to a first side of the second set of 8 cores; (e) a first search port integrated to a second side of the first set of 8 cores; (f) a second search port integrated to a second side of the second set of 8 cores; (g) a first set of 8 interlock signals, and (h) a second set of 8 interlock signals.
One of the first set of 8 interlock signals is provided for each core of the first set of 8 cores, the first set of 8 interlock signals is integrated from the first search port to the first maintenance port to signal when reads and writes are to be performed to selected ones of the first set of 8 cores, and the reads and writes are configured to be performed without interrupting consecutive searches by the first search port. Similarly, one of the second set of 8 interlock signals is provided for each core of the second set of 8 cores, the second set of 8 interlock signals is integrated from the second search port to the second maintenance port to signal when reads and writes are to be performed to selected ones of the second set of 8 cores, and the reads and writes configured to be performed without interrupting consecutive searches by the second search port.
In still another embodiment, a content addressable memory is disclosed. The content addressable memory includes a search port for performing search operations. A maintenance port for writing and reading data to address locations of the content addressable memory is also provided. An interlock signal is configured to be communicated from the search port to the maintenance port to establish when writing and reading of data is to be performed to the content addressable memory without interrupting search operations that can be triggered at each clock cycle.
The advantages of the present invention are numerous. Most notably, the search port of the present invention is configured to perform continuous searches on each cycle and the maintenance port is configured to perform writes, reads, resets and other maintenance operations without disturbing the search operations. In a preferred embodiment, the search port is configured to communicate an interlock signal to indicate when search operations have been completed and to indicate when reads or writes are to be performed. Preferably, the maintenance operations are performed during the pre-charge of a search operation. Therefore, even though the maintenance port receives interlock signals from the search port, the maintenance port and the search port operate independently and in parallel with one another.
Other advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.